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| d a t a sh eet preliminary speci?cation supersedes data of 1995 oct 11 file under integrated circuits, ic18 1996 jun 19 integrated circuits p82c150 can serial linked i/o device (slio) with digital and analog port functions
philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 1996 jun 19 2 contents 1 features 2 general description 3 ordering information 4 block diagram 5 functional diagram 6 pinning information 6.1 pinning 6.2 pin description 7 functional description 7.1 i/o functions 7.2 i/o registers 7.3 can functions 7.4 initialization 7.5 p82c150 operation after reset or change of bus mode 8 limiting values 9 dc characteristics 10 ac characteristics 11 application information 11.1 maximum bus length 11.2 start up sequence 11.3 external oscillator mode 11.4 using digital i/o port functions 11.5 using dpm 11.6 using adc 11.7 using analog input port functions 11.8 can-bus system applications 12 package outline 13 soldering 13.1 introduction 13.2 reflow soldering 13.3 wave soldering 13.4 repairing soldered joints 14 definitions 15 life support applications 1996 jun 19 3 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 1 features single-chip i/o device with can protocol controller meets can protocol specification version 2.0 a and b (passive) with restricted bit timing fully integrated clock oscillator (no crystal required) 16 configurable digital or analog i/o port pins each of the port pins individually configurable via can-bus: port direction, port mode and event capture facilities for inputs (event driven or polling) up to sixteen digital inputs; automatic transmission of a can message on a change on inputs individually selectable up to sixteen 3-state outputs up to two quasi-analog outputs with 10-bit accuracy 10-bit analog-to-digital converter with up to six multiplexed analog input channels (for accuracy see section 11.6) two general purpose comparators bit rate from 20 kbit/s up to 125 kbit/s using internal oscillator automatic bit rate detection and calibration up to sixteen p82c150 nodes for one can-bus system four identifier bits programmable slio functions controlled by a single intelligent node (host) sleep-mode with wake-up via can-bus differential can-bus input comparator and can-bus output driver supply voltage: 5 v 4% operating temperature: two ranges - 40 to +85 c and - 40 to +125 c. 2 general description the p82c150 is a single-chip 16-bit i/o device including a controller area network (can) protocol controller with automatic bit rate detection and calibration. it features 16 configurable i/o port pins with programmable direction, digital and analog modes. the p82c150 provides a configurable event capture facility supporting automatic transmission caused by a change on the port input pins. the clock oscillator requires no external components, thus, the cost of the can link is reduced significantly. the p82c150 is a very cost-effective way to increase the i/o capability of a microcontroller based can node as well as to reduce the amount and complexity of wiring. advanced safety is provided by the can protocol. applications: body electronics and instrumentation in automotive applications sensor/actuator interface in automotive and general industrial applications extension of i/o capabilities of microcontroller based can nodes. 3 ordering information type number package temperature range ( c) name description version p82c150 aft so28 plastic small outline package; 28 leads; body width 7.5 mm sot136-1 - 40 to +85 p82c150 aht - 40 to +125 1996 jun 19 4 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 4 block diagram fig.1 block diagram. handbook, full pagewidth p82c150 error management logic rxo 21 rx1 22 19 18 bit stream processor input comparator transmit/ receive logic port logic identifier latch 23 4 20 oscillator and calibrator clock 8 ref av dd v dd +5 v +5 v 9 to 16 5, 6, 7 1, 2, 3 p8 to p15 p5 to p7 p2 to p4 p0/clk, p1 av ss mha064 can-bus can-bus 17 p16 xmod 25 26 tx1 tx0 rst 16 i/o port pins 1 / 2 av dd + reference voltage 27, 28 bus mode bus mode i/o registers 24 v ss 1996 jun 19 5 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 5 functional diagram fig.2 functional diagram. handbook, full pagewidth p82c150 ref rx0 rx1 tx0 p15 p13 p14 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0/clk rst (reset) xmod can-bus inputs analog-to-digital comparator input comparator inputs 16-bit digital i/o mha066 tx1 p16 can-bus outputs adc feedback output multiplexed analog- to-digital signal analog input dpm1 output analog inputs, analog switches dpm2 output identifier programming reference voltage output v ss av ss v dd av dd 1996 jun 19 6 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 6 pinning information 6.1 pinning fig.3 pin configuration. handbook, halfpage 26 27 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 p82c150 14 28 25 mha065 p2 p3 p4 v ss xmod p6 p5 p7 v dd p8 p9 p10 p11 p12 p13 p1 p0/clk tx1 av ss tx0 rst rx1 rx0 av dd ref p16 p15 p14 1996 jun 19 7 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 6.2 pin description table 1 pin description for p82c150; so28; see note 1 note 1. in this documentation the port pins are referred to by their symbols, not by their pin number. for example p15 means i/o port 15 at pin 16. symbol pin description p2 1 i/o ports p2 to p3; identi?er programming input. p3 2 p4 3 i/o port 4; dpm2 output. v ss 4 ground , digital part (0 v; logic circuits and can-bus driver). p5 5 i/o ports p5 to p6; analog input. p6 6 p7 7 i/o port 7; analog input or analog-to-digital comparator 1 output. v dd 8 power supply, digital part (+5 v; logic circuits and can-bus driver). p8 9 i/o port 8; analog input or comparator 3 output. p9 10 i/o port 9; analog input or comparator 2 output. p10 11 i/o port 10; comparator 3 inverting input or dpm1 output. p11 12 i/o port 11; comparator 3 non-inverting input. p12 13 i/o port 12; comparator 2 inverting input. p13 14 i/o port 13; comparator 2 non-inverting input. p14 15 i/o port 14; multiplexed analog signal. p15 16 i/o port 15; analog-to-digital comparator input. p16 17 feedback output of analog-to-digital converter. av dd 18 power supply, analog part (+5 v; can input, oscillator and reference). ref 19 reference voltage output ( 1 2 av dd ). av ss 20 ground , analog part (0 v; can input, oscillator, reference). rx0 21 can-bus input. rx1 22 rst 23 external reset input (active-high) for internal oscillator mode; pulled to + 5 v for external oscillator mode (see section 11.3). xmod 24 connected to gnd for internal oscillator mode ; external reset input (active-low) for external oscillator mode (see section 11.3). tx0 25 open-drain can-bus output: dominant = low; recessive = ?oating. tx1 26 open-drain can-bus output: dominant = high; recessive or at bus mode 2 ?oating. p0/clk 27 i/o port p0 , identi?er programming input in internal oscillator mode; clock input in external oscillator mode (see section 11.3). p1 28 i/o port p1; identi?er programming input. 1996 jun 19 8 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7 functional description 7.1 i/o functions the p82c150 provides 16 port pins (p15 to p0) which are individually configurable via can-bus. besides the digital i/o functions some of these port pins provide analog i/o functions. 7.1.1 d igital input functions input levels high and low on the port pins (p15 to p0) can be read in two ways by the host node: polling: a remote frame is sent to the p82c150 to be answered by a data frame containing the data input register contents. event capture: in case of edge-triggered mode, the p82c150 sends the same data frame caused by the event of a rising and/or falling edge on the corresponding port pins (see table 3). 7.1.2 d igital output functions the data output register is set via a can message. its content is only output when the corresponding bits of the output enable register are set to logic 1s. 7.1.3 a nalog input / output functions up to six multiplexed analog input signals for analog-to-digital conversion or general purpose up to two quasi-analog output channels (dpm; distributed pulse modulation) two input comparators, for example for window comparator applications a separate analog-to-digital input comparator with feedback output. analog-to-digital converted digital results are obtained by reading the analog-to-digital conversion (adc) register. analog functions of each port pin are individually controlled by the analog configuration register. writing the i/o registers is done serially via can-bus by data frames. the first data byte contains the register address, and the second and third data bytes represent the register contents. if a read only register is addressed, the contents of the second and third data bytes are ignored. it is recommended to set unused port pins to high (100 k w resistor to v dd ). fig.4 i/o port pins. handbook, halfpage px mha068 dix dox oex 3-state buffer p82c150 1996 jun 19 9 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.2 i/o registers table 2 i/o register map 15 (msb) 1413121110987654321 0 (lsb) a ddress 0: d ata i nput di15 di14 di13 di12 di11 di10 di9 di8 di7 di6 di5 di4 di3 di2 di1 di0 a ddress 1: p ositive e dge pe15 pe14 pe13 pe12 pe11 pe10 pe9 pe8 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 a ddress 2: n egative e dge ne15 ne14 ne13 ne12 ne11 ne10 ne9 ne8 ne7 ne6 ne5 ne4 ne3 ne2 ne1 ne0 a ddress 3: d ata o utput do15 do14 do13 do12 do11 do10 do9 do8 do7 do6 do5 do4 do3 do2 do1 do0 a ddress 4: o utput e nable oe15 oe14 oe13 oe12 oe11 oe10 oe9 oe8 oe7 oe6 oe5 oe4 oe3 oe2 oe1 oe0 a ddress 5: a nalog c onfiguration adc oc3 oc2 oc1 0 m3 m2 m1 sw3 sw2 sw1 0 0 0 0 0 a ddress 6: dpm1 dp9dp8dp7dp6dp5dp4dp3dp2dp1dp0000000 a ddress 7: dpm2 dq9dq8dq7dq6dq5dq4dq3dq2dq1dq0000000 a ddress 8: a nalog - to -d igital c onversion (adc) ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 0 0 0 0 0 1996 jun 19 10 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.2.1 d ata i nput r egister (a ddress 0) this read only register contains the states of port pins p15 to p0 which are transmitted on request, or automatically by change of one of the input levels, provided that the respective input is configured to event capture mode (see table 3). when an edge is detected the port state is loaded into the transmit buffer after the control field of the triggered message is sent. therefore a delay for input settling is provided. if between edge detection and transmission of the data input register another input signal change at the input port occurs, the corresponding data input register bit is overwritten by the current input port value. additionally the register content is sent automatically after wake-up or bus mode change, once the bit time has been calibrated (part of the sign-on message). 7.2.2 p ositive e dge r egister (a ddress 1) this write only register contains configuration information per port pin for the event capture facility. the corresponding pe-bit (see table 3) has to be set to logic 1 to enable capturing of the rising edge. 7.2.3 n egative e dge r egister (a ddress 2) this write only register contains configuration information per port pin for the event capture facility. the corresponding ne-bit (see table 3) has to be set to logic 1 to enable capturing of the falling edge. the combination of pe and ne functions is possible. 7.2.4 d ata o utput r egister (a ddress 3) this write only register contains the output data for the port pins. the output drivers are bitwise enabled by oe (see section 7.2.5). new data for the output port register are processed and written to the output ports directly after the corresponding can message to the p82c150 is successfully checked and becomes valid. 7.2.5 o utput e nable r egister (a ddress 4) this write only register controls the output drivers of the port pins. the corresponding output enable register bit has to be set to logic 1 to enable an output driver. if set to logic 0, the corresponding output driver is disabled (floating; see fig.7). table 3 programming of the i/o registers to event capture on edge or to digital output x = don t care; n=0to15. function register contents of particular port pin positive edge (bits pen) negative edge (bits nen) output enable (bits oen) digital output x x 1 digital input polling x x x event capture on edge rising 1 0 x falling 0 1 x rising and falling 1 1 x 1996 jun 19 11 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.2.6 a nalog c onfiguration r egister (a ddress 5) this read/write register contains the bits adc, oc3 to oc1, m3 to m1 and sw3 to sw1 (see fig.7). adc bit (analog-to-digital conversion start bit; write only bit). the p82c150 starts an analog-to-digital conversion cycle at adc = 1 ended with the transmission of a message containing the result. after that, the adc bit is reset automatically. oc3 to oc1 bits (comparator output data; read only bits). the bits oc3 to oc1 represent the logical output level of the analog comparators at input port pins p10, p11, p12, p13 and p15. the p82c150 sends back the logical output value of these comparators after having received a data frame (see section 7.3.3) addressing the analog configuration register. the comparator outputs can be monitored at the output port pins p8, p9 and p7. m3 to m1 bits (multiplexer control bits; write only bits). the logical value of the comparators is monitored on port pins p8, p9 and p7 (see fig.7) by setting m3 to m1 to logic 1, provided that these pins are configured as outputs (oe = 1). additionally the register content is sent automatically when the corresponding port bits in the positive edge register and/or negative edge register and the corresponding bits in the output enable register are set. sw3 to sw1 (analog switch control bits; write only bits). one of the analog switches s1 to s6 can be closed by setting the switch bits to the corresponding value (see fig.7 and table 4). table 4 analog switch selection by sw3, sw2, sw1. note 1. evidently if p14 is driven, it may not be connected to any other driven pin via the internal analog switches (avoid short-circuit!). sw3 sw2 sw1 switch state 0 0 0 no switch closed (s0); note 1 0 0 1 s1 closed 0 1 0 s2 closed 0 1 1 s3 closed 1 0 0 s4 closed 1 0 1 s5 closed 1 1 0 s6 closed 1 1 1 reserved 7.2.7 dpm1 r egister (a ddress 6) this write only register contains data for a quasi-analog output signal on port pin p10, which is generated by distributed pulse modulation (dpm; see fig.9). the output enable bit must be set for this functions (oe10 = 1). the dpm1 output signal is inverted by setting do10 = 1. the number of output pulses during a dpm period is given by the dpm1 register value. these pulses have 4 t clk length and are distributed over the dpm period. an analog voltage is provided after smoothing the output signal by an external rc combination. 7.2.8 dpm2 r egister (a ddress 7) this write only register contains data for a quasi-analog output signal on port pin p4. the function of the dpm2 corresponds to the definition of dpm1. 7.2.9 a nalog-to- d igital c onversion (adc) r egister (a ddress 8) this read only register contains the result of the analog-to-digital converted level of that i/o pin which was selected by the sw bits. the conversion is started by adc-bit set to logic 1 (see section 7.2.6), or by transmitting a data frame addressing the adc register. 1996 jun 19 12 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 fig.5 analog configuration of i/o port pins; r1, r2 and c1 are used to implement the analog-to-digital converter. o k, full pagewidth 15 3 p82c150 7 6 5 9 10 16 17 r1 r2 c1 1 / 4 f clk adc register oc1 s0 s2 s3 s4 s5 s6 p13 13 12 11 dpm1 dpm2 oc2 oc3 m3 m2 m1 mha067 p16 p15 p14 p7 p6 p5 p8 p9 14 p12 p11 p10 p4 s1 sw3 to sw1 = 1 = 1 1 / 2 v dd do7 do8 do9 do4 do10 oe7 oe8 oe9 oe10 oe4 + - + - + - 1996 jun 19 13 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 fig.6 dpm output pulses at do10(4) = 0; output pulses are inverted at do10(4) = 1. handbook, full pagewidth l h l h l h l h l h l h l h t dpm = 1024 x 4 t clk 4 t clk dpm = 0 dpm = 1 dpm = 2 dpm = 3 dpm = 512 dpm = 513 dpm = 1023 mha081 distributed pulse modulation (dpm) is a special pulse count modulation. 1996 jun 19 14 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.3 can functions the p82c150 meets the can protocol specification version 2.0 a and b (passive) with restricted bit timing because of the on-chip rc-oscillator and the automatic bit rate detection. in a system with p82c150 nodes there must be at least one conventional crystal-driven can controller (host node) which is compatible to the can specification v1.2 or later to control p82c150 nodes. host nodes compatible to can specification v1.1 can also be used provided that the p82c150 nodes are powered by a high-accuracy power supply or they are in external oscillator mode (refer to section 11.3). each time a p82c150 node receives a data frame, it initiates the transmission of a data frame containing four bits status information, the register address (previously received) and the current contents of the addressed register (exception: see section 7.3.3.1). this enables the host node to verify that the addressed register has correctly been written in case of writeable registers, and to read the contents in case of readable registers. 7.3.1 can i dentifier data and remote frames to be processed by the p82c150 are of standard format with 11 identifier bits id.10 to id.0. frames with extended identifier (can specification version 2.0 b) are ignored. the way of identifier programming is based on two facts: each p82c150 operates with only two identifiers distinguished by the lsb (see tables 5, 6 and 7). the identifier with the higher priority is used for data frame reception. an extra identifier is used for calibration purposes. there can be maximum sixteen p82c150 circuits in one network. table 5 message types and format note 1. dlc = data length code; dir = lsb of identifier (see section 7.3.1). table 6 standard format identi?er bits id.10 to id.0 1 = recessive; 0 = dominant table 7 description of the standard format identi?er bits frame transmission by 82c150 reception at 82c150 data frame yes (dlc = 3; dir = 1) yes (dlc = 3; dir = 0; calibration message with dlc = 2 to 8 allowed, see section 7.3.10) remote frame no yes (dlc = 3; dir = 1) error frame yes yes overload frame yes (only as a response) yes identifier id.10 id.9 id.8 id.7 id.6 id.5 id.4 id.3 id.2 id.1 id.0 0 1 p3 1 0 p2 p1 p0 1 0 dir rtr bit symbol description id.8 p3 programmable identifier bits read from port pins p3 to p0 during reset. the input levels on p3 to p0, for example set by resistors to v ss or to v dd , are latched in the identifier latch with the falling edge of the rst input signal. they represent the variable part of the identifier, while the remaining bits are fixed (mask-programmed), p3 to p0 can be used as i/o ports after reset. id.5 to id.3 p2 to p0 id.0 dir dir = 1 for transmission of data frames to the host. it must be set to a logic 1 in remote frames and to a logic 0 in data frames received from the host. rtr remote transmission request bit. 1996 jun 19 15 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.3.2 t ransmission of d ata f rames data frames transmitted by the p82c150 contain three data bytes (see fig.7). the first data byte contains the status information and the register address a3 to a0 (see tables 8 and 9), the other two data bytes contain the content of the addressed i/o register. after each successful message transmission, the p82c150 delays the transmission of a possibly further pending message for three bit times. the reason is to give other can controllers - with a lower identifier priority - the possibility to transmit a message in case of faulty contact at one of the edge-triggered port pins. 7.3.3 r eception of d ata f rames and r emote f rames received data frames have the same format as transmitted ones, only the dir-bit (id.0) in the arbitration field is different. the status bits rstd, ew, bm1 and bm0 are ignored during reception. the p82c150 confirms each reception of a data frame by transmitting a data frame containing the (new) contents of the addressed i/o register. 7.3.3.1 exceptions to the rule 1. analog configuration register: if a p82c150 receives a data frame addressing the analog configuration register and the adc bit is set to logic 1, it will respond with two messages. the first message returns the contents of the analog configuration register. the control instructions are executed (e.g. next analog input channel selected), and an analog-to-digital conversion cycle is started after a set-up time. after finishing the analog-to-digital conversion cycle, the second message is transmitted containing the result (adc register). 2. adc register: on receiving a data frame addressing the adc register, the p82c150 starts an analog-to-digital conversion cycle. it automatically returns the result of the conversion (adc register) by transmitting a respective data frame after finishing the analog-to-digital conversion cycle. 3. at normal operation, the calibration messages are confirmed by returning a dominant bit in the acknowledge slot. there is no particular confirmation message returned by the p82c150. only after entering the calibrated state (start-up), a data frame (sign-on message) containing the data input register contents is transmitted indicating to the host node, that the p82c150 is now ready for transmission. 7.3.3.2 remote frame received remote frames must have the data length code dlc = 3 (remote frames with dlc 1 3 are ignored). it is answered by a data frame containing the contents of the data input register. 1996 jun 19 16 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 table 8 data frame byte 1 table 9 description of data frame byte 1 bits status register address rstd ew bm1 bm0 a3 a2 a1 a0 symbol description status rstd it is logic 1 in the ?rst message (sign-on message) after the successful detection of the bit rate (bit time calibrated). ew logic 1, if the error warning limit (32) is reached. in the sign-on message ew is always logic 1. the ew status bit is set when the receive error counter or the transmit error counter have exceeded the error warning limit of 32, also temporarily, since the last successful transmission of a message. bm1 bus mode status bits. bm0 register address a3 to a0 register address bits. fig.7 p82c150 data frame. handbook, full pagewidth mha071 0 0 1 p3 1 0 p2 p1 p0 1 0 dir rtr id0 id10 sof identifier 0 0 0 0 1 1 rstd ew bm1 bm0 a3 a2 a1 a0 reserved data length code p82c150 status register address x x x x x x x x x x x x x x x x i/o register data(15 to 8) i/o register data(7 to 0) control field arbitration field byte 1 byte 2 byte 3 sof: start of frame. rtr: remote transmission request. p3 to p0: equals programmed identifier bits. 1996 jun 19 17 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.3.4 can- bus modes the p82c150 can pass through four can-bus modes under certain conditions (see fig.8). in the bus modes 0 to 2 (see table 10) the p82c150 is operating with different input comparator configurations. bus mode 3 is the power reduced sleep mode. the bus modes support: communication on two balanced wires (differential system) communication on one wire in a two-wire differential system sleep mode with wake-up via either a dominant signal on rx0 or rx1 input connection of a second transmission medium (redundancy) there are two possibilities for condition 1 to switch to the next mode (see fig.8): overflow of the bit counter when 8192 is reached since the last calibration message overflow of the transmit error counter (>255; bus-off limit reached). when the bus mode changes, all i/o registers are cleared and outputs become floating (oe bits cleared). that means the i/o ports return to a fail-safe state whenever the p82c150 looses connection to its host controller. this is a kind of network watchdog function. the status bits are set to the following values after a bus mode change: rstd = 1 ew = 0 bm new =bm old +1. the programmed identifier bits remain unchanged. after reset the p82c150 changes directly into bus mode 3 (sleep mode). during sleep mode, the internal rc oscillator is stopped, and all the output drivers are disabled (i/o register contents cleared). a p82c150 in sleep mode can be woken up via can-bus lines (dominant level on rx0 or rx1) or by a reset condition. fig.8 can-bus modes and switch-over conditions. c olumns differential mode inputs: rx0, rx1 outputs: tx0, tx1 '0' one-wire rx1 mode input: rx1 outputs: tx0, tx1 '1' '2' sleep mode inputs: rx0, rx1 outputs: no '3' one-wire rx0 mode input: rx0 output: tx0 condition 1 condition 1 condition 1 condition 2 mha070 end of reset condition 1: bit counter overflow (>8191) or transmit error counter overflow (>255). condition 2: dominant bit detected on rx0 and rx1. table 10 can-bus modes note 1. output tx1 is disabled in bus mode 2 to tolerate short-circuit between the can-bus wires can_h and can_l. bus mode bits reception level transmission bm1 bm0 recessive dominant tx1 tx0 0 = differential 0 0 rx0 > rx1 rx0 < rx1 enabled enabled 1 = one-wire rx1 0 1 rx1 < ref rx1 > ref enabled enabled 2 = one-wire rx0 1 0 rx0 > ref rx0 < ref disabled enabled 3 = sleep 1 1 rx0 > ref and rx1 < ref rx0 < ref or rx1 > ref disabled disabled 1996 jun 19 18 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.3.5 b it t iming the nominal bit time of the p82c150 is subdivided into 10 time quanta. the synchronization time segment (sync_seg) and the propagation time segment (prop_seg) are each one time quantum long. the phase buffer segment 1 (phase_seg1) and the phase buffer segment 2 (phase_seg2) are each four time quanta long. the resynchronization jump width (sjw) is four time quanta long. the sample point is located at the end of the phase buffer segment 1. the nominal bit time is internally adjusted to that bit timing which is provided by the crystal driven host (calibration message). the usable bus length at a given bit rate is reduced in comparison to other can controllers with programmable bit timing because the propagation time segment is fixed to 1 10 length of the nominal bit time. the bit segmentation of the crystal driven host should be programmed like the fixed bit segmentation of the p82c150, e.g. one bit time segment is 1 10 length of the nominal bit time (refer also to table 15 for bit time programming). table 11 bit time subdivision 1 bit time bt1 bt2 bt3 bt4 bt5 bt6 bt7 bt8 bt9 bt10 sync_seg prop_seg phase_seg1 phase_seg2 7.3.6 can-b us t ransceiver the transceiver of the p82c150 consists of the configurable input comparator and of complementary open-drain driver outputs. the reference voltage ref is an additional output. 7.3.6.1 can-bus input comparator (rx0, rx1) the input comparator monitors the transient voltage on rx1 and rx0. the result of the input comparator is logic 1 if the voltage levels of the can-bus lines are regarded as recessive, and logic 0 if they are regarded as dominant. the recessive state and the dominant state are not equivalent and may not be mixed-up. the input comparator is configurable depending on the four can-bus modes (see table 10), supporting battery-powered applications (sleep mode) and tolerance against bus wiring failures. 7.3.6.2 can-bus output drivers (tx0, tx1) the output driver function is shown in table 12. the output driver tx1 is disabled in bus mode 2 to tolerate a short-circuit between the can-bus lines in a two-wire differential can physical layer. table 12 can-bus driver output function can output recessive dominant reset state, bus-off and sleep mode (mode 3) modes 0 and 1 mode 2 tx0 ?oating low low ?oating tx1 ?oating high ?oating ?oating 1996 jun 19 19 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.3.7 t ransmit and receive logic the transmit and receive logic stores the destuffed bit stream which was received or is about to be transmitted. the incoming identifier is compared with that of the p82c150. the content of the message is transferred to the port logic in case of matching. at transmission, the message about to be sent is put together: the identifier, the status information, the register address and the content of the addressed register from the port logic. 7.3.8 b it s tream p rocessor and e rror m anagement l ogic the bit stream processor (bsp) is a sequencer to control the data stream between the transmit/receive logic (parallel data) and the on-chip can transceiver (serial data). reception/transmission, bit stuffing/destuffing, arbitration and error detection, according to can protocol specification version 2.0 a and b (passive), are performed. further, automatic re-transmission of corrupted messages is handled by means of continuously comparing the output bit stream with the input bit stream. moreover, the bit stream processor provides control information to calibrate the internal bit time. the error management logic is responsible for the complete can-inherent error management. 7.3.9 o scillator and calibration the p82c150 contains an on-chip rc-oscillator. the bit time is automatically calibrated by messages being received via can-bus. during start-up (after wake-up or reset) any message is used to calibrate the bit time until the calibration is sufficient to receive messages correctly. from this time on, the bit time is calibrated and fine-tuned by calibration messages with a special identifier transmitted by the crystal-controlled host. only p82c150 nodes being calibrated by calibration messages can transmit messages. the first message is transmitted directly after entering the calibrated state (sign-on message). since the p82c150 is not able to transmit as long as the bit time is not calibrated, it cannot wake-up other can nodes via the bus line. hence to keep the network alive, the calibration message must be transmitted regularly by a crystal-controlled (host) node with a maximum repetition period of 8192 bit (bit length measured by the 82c150). it is recommended to select a repetition period between 3800 and maximum 8000 bit times. 7.3.10 c alibration message the calibration message has to meet the following requirements transmitted by a crystal-controlled node (host node) identifier: 000 1010 1010 (1 = recessive; 0 = dominant) rtr bit: 0 allowed control field: dl c=2to8 the first recessive to dominant transition after the control field must be followed by another recessive to dominant transition in a distance of exactly 32 bit (stuff bits included). example of a suitable calibration message (there are others using different data bytes; see table 13): data length code: 0010 1st data byte: 1010 1010 (aah) 2nd data byte: 0000 0100 (04h). table 13 example of a suitable calibration message the two important 1/0 transitions are marked by underlines; see note 1. note 1. i = stuff bit (recessive); the total length is 67 bit from start-of-frame to end-of-intermission. sof arbitration field control field data byte 1 data byte 2 crc field 0 000 1010 1010 0 000 i 010 1010 1010 0000 i 0100 000 i 0 1011 1000 00 i 0 1996 jun 19 20 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.4 initialization 7.4.1 i dentifier programming most of the p82c150 identifier bits are fixed. four bits are programmable via port pins p3 to p0. all output drivers are disabled at reset, also p3 to p0. thus the outputs are floating unless the input level is defined by external components to define identifier bits. they are latched at the end of reset, and p3 to p0 can be used as port pins. it is not allowed, according to the can protocol specification, that multiple bus nodes transmit the same identifier bit combination. therefore a p82c150 must have one of the 16 possible identifier bit combinations, one that is not yet occupied. 7.4.2 r eset function rst = high disables all output drivers p16 to p0, tx0 and tx1. all i/o registers are automatically cleared and set to logic 0. the bit time is set greater than 50 m s. if a particular clock period is necessary, e.g. for a dedicated dpm output frequency, this can be achieved by feeding an external clock signal into p0. rst and test must be permanently high for this special mode. a reset is then performed as usual (rst = high; test = low). table 14 situation after reset 7.4.3 b it time calibration the p82c150 must receive at least three messages to calibrate its bit time after reset or change of bus mode. the first message is used to detect the bit time length (rough calibration) between two consecutive falling edges at the output of the can input comparator. therefore the bit stream should contain a sequence of 1010. status bits identifier bits rstd = 1 id.8 equals p3 ew = 1 id.5 equals p2 bm1 = 0 id.4 equals p1 bm0 = 0 id.3 equals p0 after rough calibration the p82c150 can receive any valid can message correctly and executes respective commands without giving an acknowledge. with another valid can message and additionally with one valid calibration message the p82c150 is fully calibrated and sends its sign-on message. as long as the p82c150 is fully calibrated the p82c150 acts as an active can node. the p82c150 treats any can message (including the calibration message) as a valid message, when these messages are terminated by an error passive frame because of a missing acknowledge. this situation may occur whenever a host node works together with p82c150s and the host node doesnt receive an acknowledge as long as the p82c150s are not fully calibrated. 7.4.3.1 sign-on message this special data frame is transmitted once by the p82c150 after entering the calibrated state. it indicates to the host node that the p82c150 is ready for transmission. the sign-on message returns the contents of the data input register, and can be recognized by the host mode by checking the rstd status bit: sign-on message rstd = 1 other data frames rstd = 0 note that in the sign-on message the ew bit is logic 1. nevertheless the p82c150 status with the error counters are set to logic 0. 1996 jun 19 21 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 7.5 p82c150 operation after reset or change of bus mode figure 9 illustrates the calibration procedure of the p82c150 after power-on-reset or after a bus mode change. a ndbook, full pagewidth p82c150 receives calibration message within 8192 bit times after wake-up or bus mode change p82c150 is fine calibrated and i/o register cleared bus mode change e.g. due to missing reception of a calibration message within 8192 bit times end of power-on-reset id bits from p0-p3 latched i/o registers cleared p82c150 receives 1st message (any message) p82c150 receives 2nd message (any message), acknowledge not required but no active error flag allowed p82c150 waits until bus-off recovery sequence finished p82c150 sends 'sign-on' message p82c150 is roughly calibrated and has started bus-off recovery sequence (counting 129 blocks of 11 recessive bits) rough calibration verified p82c150 is on bus and ready to send after bus-of f sequence finished communication with host node possible mha080 fig.9 slio operation flow after reset and bus mode change. 1996 jun 19 22 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 8 limiting values in accordance with the absolute maximum rating system (iec 134). symbol parameter min. max. unit v dd supply voltage on v dd pin - 0.5 +6.5 v v i dc input voltage on any pin (rx0, rx1, tx0, tx1 excluded) - 0.5 v dd + 0.5 v i i rx1 and rx0 input current - 2ma i ref reference output current - 2ma i o port output current at port enabled (pins p0 to p15) - 5ma port output current at analog switch enabled (oe-bits = 0; pins p5 to p9, p13, p14) - 7.5 ma tx0 and tx1 output current - 30 ma p otot total power dissipation (port outputs together) - 200 mw t amb operating ambient temperature range: - 40 +125 c t stg storage temperature range - 65 +150 c p tot total power dissipation - 1w 1996 jun 19 23 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 9 dc characteristics v dd =5v 4%; v ss =0v; t amb = - 40 to +85 c and t amb = - 40 to +125 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit supply v dd supply voltage note 1 4.8 5.2 v i dd operating supply current v rst =v dd ; all port inputs connected via 1 m w to gnd - 22 ma i dd(sm) supply current sleep mode ports p15, p13 and p11 connected to v dd ; ports p12 and p10 connected to v ss ; all other port inputs connected via 1 m w to gnd 1ma can input comparators rx0 and rx1 v dif differential input voltage 0.3av dd 1996 jun 19 26 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 fig.11 p82c150 start-up bit time calibration procedure for host node (p8xc592, p8xce598 or p82c200) . handbook, full pagewidth if if load calibration message into transmit buf fer j := 18 else else then else j : = j - 1 if j = 0 wait for reception of sign-on message from p82c150 nodes from now onwards transmit calibration message periodically with a recommended repetition period between 3800 and 8000 bit times then then mha079 '0' set bit 'transmission request' (cmr.0) in command register set bit 'abort transmission' (cmr.1) in command register 'transmit status' = 0 (1) 'transmit status' = 1 (1) (1) bit sr.5 in status register. 1996 jun 19 27 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 11.3 external oscillator mode in this mode the p82c150 operates with an external clock instead with the on-chip rc-oscillator. figure 14 shows the application with an external clock. in this mode the p82c150 can achieve bit rates below 20 kbit/s and above 125 kbit/s. the dpm pulse width is 4 t clk of the external clock. the corresponding can identifier bit at port p0 is set to a logic 0. therefore only eight p82c150 based can nodes operate within the same network in external oscillator mode. 11.3.1 n ote the external oscillator mode is not the normal operation mode. 11.4 using digital i/o port functions figures 12 and 13, show the principle application for digital input and output. 11.5 using dpm the simplest way to generate an analog voltage using the p82c150 is to apply an external low pass filter at one of the dpm (distributed pulse modulation) outputs. the simplest implementation concept is a rc-filter of the first order (refer to fig.15). regarding the selection of the time constant (edge frequency) of this filter, a trade-off between minimizing of the ripple voltage for maximum accuracy and minimum of the settling time has to be considered. fig.12 example for digital input application. p82c150 + 5 v p0 to p15 digital input mha072 fig.13 example for digital output application. p82c150 digital output p0 to p15 mha073 fig.14 p82c150 in external oscillator mode. handbook, halfpage p82c150 reset mha078 clock p0/clk xmod rst + 5 v fig.15 example for dpm application. p82c150 analog output dpm1(2) p10(p4) v t v t mha074 if the output is loaded by a resistive load, this will decrease the accuracy due to the voltage drop across the series resistor. in these cases a low value for the series resistor should be chosen. the repetition time of one dpm cycle can be derived from: t cyc 4096 f osc ------------ - = 1996 jun 19 28 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 11.6 using adc the application in fig.16 can be used for analog-to-digital conversion for only one analog input signal. the evaluation of adc were done with the values r1 = r2 = 100 k w and c = 3.3 nf; under these conditions the adc may reach an accuracy of 7 to 8 bit (depends on application). the external components should be connected close to the port pins p15 and p16 with short wiring to avoid disturbances at the analog input port pin p15. using the on-chip multiplex function the p82c150 provides up to six input port pins to convert analog input signals to digital values (see fig.17). the period for one adc cycle is identical to the length of one dpm cycle. 11.7 using analog input port functions figure 18 shows the wide range of analog input applications: comparison of two analog input signals. comparison of one analog input signal against a fixed threshold. window comparator including monitoring the comparator outputs at the port pins p8 and p9; additional automatically generated messages, when the corresponding port bits in the negative edge and/or positive edge register are set. local control two-step system. fig.16 adc implementation. handbook, halfpage p82c150 p16 r1 r2 c p15 one analog input signal for a/d conversion mha076 fig.17 two multiplexed analog input signals switched for analog-to-digital conversion (maximum 6 signals; see fig.5). handbook, halfpage p82c150 feedback p15 p16 p14 analog signal p5 p6 v t v t mha075 sw3 to sw1 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 1996 jun 19 29 fig.18 examples of comparator applications. d book, full pagewidth mha082 p82c150 v t v t p11 (p13) p10 (p12) p82c150 v t p11 (p13) p10 (p12) m3 (m2) +5 v threshold comparator p8 (p9) output enabled and edge-triggered mode (pe and/or ne set) v comparison between two analog input signals message transmission when analog input signal exceeds upper respectively lower threshold voltage (window comparator) p82c150 v t p13 p12 +5 v upper threshold sensor signal p8 v t v t p9 p11 p10 comparators m3 lower threshold m2 message transmission when analog input signal exceeds threshold voltage p82c150 t p11 (p13) p10 (p12) m3 (m2) +5 v threshold comparator p8 (p9) output enabled v t to actuator local two-step control system sensor signal output enabled and edge-triggered mode (pe and/or ne set) output enabled and edge-triggered mode (pe and/or ne set) oc3 (oc2) oe8 (oe9) do8 (do9) do8 oe8 do9 oe9 di9 di8 oe8 (oe9) do8 (do9) di8 (di9) di8 (di9) philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 1996 jun 19 30 fig.19 examples of topfet applications with p82c150. handbook, full pagewidth p82c150 rx0 rx1 tx0 tx1 ref +5 v rst v ss v dd buk105-50s load p w d s i linear control with status feedback buk101-50gs v bat load d s i on/off control km110bh/21-90 angle measurement +5 v v o v s gnd +5 v 10 k p v (digital out) (analog in) p y p x p z (digital in) (digital out) (dpm) v bat pf mha083 1996 jun 19 31 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 11.8 can-bus system applications handbook, full pagewidth p8xc592 / p8xce598 can-controller mha069 crx0 p82c150 pca82c250 crx1 r ext = 0 ctx0 px,y xtal1 xtal2 rx0 rx1 6.8 k w 3.6 k w 560 w 124 w tx0 + 5 v + 5 v tx1 rxd canh can bus line canl rs txd v ref topfet (1) topfet m motor lamp analog digital sensor 124 w pca82c250 rxd canh canl rs txd v ref fig.20 p82c150 system application using can transceiver pca82c250 (iso/dis 11898 standard). (1) topfet = temperature and overload-protected field-effect-transistor 1996 jun 19 32 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 12 package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot136-1 91-08-13 95-01-24 x 14 28 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a e 15 1 (a ) 3 a y 0.25 075e06 ms-013ae pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.71 0.69 0.30 0.29 0.050 1.4 0.055 0.42 0.39 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale so28: plastic small outline package; 28 leads; body width 7.5 mm sot136-1 1996 jun 19 33 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 13 soldering 13.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these cases reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 13.2 re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 13.3 wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds at between 270 and 320 c 1996 jun 19 34 philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 14 definitions 15 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. philips semiconductors preliminary speci?cation can serial linked i/o device (slio) with digital and analog port functions p82c150 1996 jun 19 35 notes internet: http://www.semiconductors.philips.com/ps/ (1) address content source june 20, 1996 philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca49 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 83749, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220 - 5th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. +380 44 476 0297/1642, fax. +380 44 476 6991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 708 296 8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 825 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 805 4455, fax. +61 2 805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 708 296 8556 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 615 800, fax. +358 615 80920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 52 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros, tel. +30 1 4894 339/911, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 648 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +1 800 234 7381, fax. +1 708 296 8556 middle east: see italy printed in the netherlands 617021/1200/02/pp36 date of release: 1996 jun 19 document order number: 9397 750 00918 |
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